A traditional phase-locked loop (PLL) used an analog, charge-pump-based design. In an analog PLL, the PLL output signal is divided down in frequency to form a feedback signal. A phase detector pulses an up or a down signal proportionally to a phase difference between the feedback signal and a reference signal. A charge pump responds to the pulsing of the up and down signals to either charge or decrease a control signal such as a control voltage, which is then filtered in a loop filter. A VCO responds to the filtered control voltage to drive the PLL output signal. The resulting feedback keeps the PLL output signal phase aligned with the reference signal. But such an analog design requires relatively large capacitors that are implemented using the metal layers adjacent the integrated circuit die. An analog PLL thus consumes a relatively large amount of die space. The relatively large capacitance also increases the time-to-lock. Moreover, analog designs are difficult to port from one process technology node to another.
Digital PLLs have thus been developed in which the phase detector output is converted to a digital number that is proportional to the phase difference between the reference signal and the feedback signal. The digital number resulting from the phase comparison is digitally filtered to provide a filtered digital signal that is converted into an analog signal such as a control current for driving a current-controlled oscillator (CCO). Alternatively, a control voltage may be produced. The resulting output signal from the oscillator forms the PLL output signal. A digital PLL thus does not require a charge pump or an analog filter. The relatively large capacitors necessary for these analog components are thus unnecessary in a digital PLL, which increases density. Moreover, a digital PLL does not suffer from the process variations for the RC components in the charge pump and analog loop filter. In addition, a digital PLL has faster lock time and may be readily ported across technology nodes. The digital filter parameters for a digital PLL are also readily adjusted to accommodate design changes.
Although a digital PLL thus has advantageous properties with regard to a traditional analog PLL, challenges remain in digital PLL design. For example, a digital PLL requires a time-to-digital converter (TDC) circuit to perform the quantization of the phase detector output signals. But the quantization by the TDC circuit results in undesirable spurs such that the TDC circuit requires pico-second accuracy to minimize the phase noise for the PLL output signal. In addition, the delay elements in the TDC circuit are subject to undesirable process variations.
Accordingly, there is a need in the art for improved PLL architectures.